Silicon integrated circuits are well known in the art for driving LCDs. Prior art drivers which are fabricated separately from the LCD may be manufactured with transistor characteristics which can be matched reasonably well, and operational amplifier type feedback circuitry can be used to reduce the gain and offset variations between channels.
It is also known in the prior art to incorporate drivers for AMLCDs directly on the LCD glass. Integral drivers have been designed in an effort to eliminate expensive prior art separate driver integrated circuits (ICs) and unreliable edge interconnections between the drivers and AMLCDs, thereby reducing overall system cost and size of the optical heads incorporating the AMLCDs.
However, it is not a simple matter to design such integrated drivers since it is difficult to manufacture TFT operational amplifiers as the output stages would be required to consist of plural TFTs connected in series across the power rails. It would not be possible to prevent all of the series pairs of TFTs on such an integrated driver from conducting simultaneously. This would result in non-uniformity and poor performance in some cases would short circuit the power supply.
There have been several approaches suggested in the prior art for the design of integrated TFT (Thin Film Transistor) gate drivers. A gate driver functions basically as a shift register. Consequently, prior art integrated gate drivers have been designed using drain clocking circuitry for achieving low power dissipation in NMOS CdSe TFTs comparable to that normally associated with CMOS devices. One such prior art driver is set forth in an article of Schleupen, K., et al. entitled "An Integrated 4-bit Gray-Scale Column Driver for TV AMLCDs", 1994 SID Digest (Society for Information Display).
However, there has been less progress in the prior art toward a consensus on the design of TFT source drivers for AMLCDs. Indeed, there are presently two distinct approaches to the design of source drivers: digital and analog. Existing digital source drivers are known for providing multiple bit outputs (eg. a 4 bit digital driver can be implemented using four large capacitors and 21 TFTs), which are sufficient for low amplitude resolution applications such as aircraft instruments or simple on/off checklist displays. Although digital drivers are expandable to a larger number of bits, the device size approximately doubles for each added bit. By way of contrast, a single analog driver can be designed which is suitable for any size of display. Such a design should utilize no resistors, should be capable of implementation in NMOS enhancement mode and must be compatible with the active matrix TFTs (ie. identical thickness of semiconductor material).
A source driver comprises three basic functional blocks: an input video multiplexer, a storage device, and an output drive stage. The input video multiplexer and storage device may be connected in series or may effectively be connected in parallel if a double buffered sample-and-hold (S/H) is provided.
In the parallel embodiment, two or more S/Hs per output line, requiring one TFT per S/H, are addressed for writing on alternate lines and reading on other lines in accordance with the display pixel format and the video input format. The output of the S/Hs are multiplexed onto one output driver by additional TFTs, one per S/H, requiring four TFTs for the minimum implementation.
For the series embodiment, the input S/Hs are loaded in succession after which the stored data is loaded broadside into another parallel S/H which functions as an analog register. The series embodiment reduces the device input capacitance and only requires two TFTs for the minimum implementation but reduces the voltage to the driver since the charge on the first S/H must also drive the second S/H without amplification. The second TFT must be characterized by a low resistance for transferring the charge in a short deadtime between switching since the first row of TFTs cannot be permitted to receive signal again until the transfer has been completed. The capacitors in the series S/H topology need only be of sufficient size to provide drive current for the duration of one line since that is all the storage time that is needed. However, the presence of two series stages tends to increase the switching noise. The double-buffered S/H needs twice the capacitance since data loaded at the beginning of one line must be retained through the end of the next line.
The design of the output drive stage must take into consideration a number of criteria and limitations dictated by the requirements for integration with the display. An essential feature of the output driver stage is that it must provide accurate output for any load while remaining independent of TFT threshold voltage.
Digital and analog drivers have been proposed which use a capacitive output drive. However, these prior art designs are non-scalable to different direct-view applications since the output capacitor must be much larger than the combined capacitance of the source line and pixel capacitance (with one line of array TFTs on). Therefore, these prior art source drivers are restricted to use with very small displays for either projection or helmet-size direct viewing.